The present invention relates to a quantum thin line producing method for forming a quantum thin line constructed of a metal or semiconductor that is minute enough to cause a quantum size effect on an insulating substrate or a semiconductor substrate via an insulating layer and to a semiconductor device employing this quantum thin line.
The large-scale integrated circuits (LSIs) that have supported the development of electronics and currently become the industrial nucleus have made great strides in terms of their performances toward larger capacity, higher speed, lower consumption of power and so on through the microstructural progress thereof. However, it is considered that the conventional device reaches the limit in terms of the principle of operation when the device size becomes 0.1 .mu.m or smaller, and accordingly, there are conducted energetic researches on a new device based on a new principle of operation. As for this new device, there is a device having a microstructure called the nanometer-size quantum dot or quantum thin line. The nanometer-size quantum dot is energetically examined together with a variety of quantum effect devices, particularly for the application thereof to a single electron device utilizing the Coulomb blockade phenomenon. The nanometer-size quantum thin line is expected to be applied to a super-high-speed transistor utilizing the quantum effect.
Particularly, in regard to the nanometer-size quantum thin line, there is carried out trial production of a semiconductor quantum device based on a new principle of operation that the degree of freedom of an electron is limited by confining the electron in a semiconductor layer having a width approximately equal to that of the electron wavelength (de Broglie wavelength) in a semiconductor crystal and by utilizing a quantization phenomenon caused by this. That is, the wavelength of an electron in a semiconductor layer is about 10 nm. Therefore, it is theoretically derived that, if the channel width is about the wavelength (width: 10 nm) of an electron, then the electron can move in this thin line while being scarcely deviated, for the achievement of the increased mobility of the electron.
Therefore, by forming a conductive layer in which a number of quantum thin lines as described above are arranged in a plane and controlling the number of electrons inside this conductive layer by the operation of a gate electrode, there can be produced a quantum thin line transistor having a higher operating speed than the conventional transistor. By incorporating a number of quantum thin lines as described above into a laser light emitting layer, there can be obtained a high-efficiency semiconductor laser device that has a sharp spectrum and excellent high-frequency characteristics even with a small injection current.
Conventionally, as a method for forming the aforementioned quantum thin line, there have been proposed methods as disclosed in the following reference documents (1) through (3).
(1) Japanese Patent Laid-Open Publication No. HEI 5-55141.
FIGS. 9A through 9E are process charts showing the "Method for producing Si thin line on SOI (silicon-on insulator) substrate utilizing anisotropic etching" disclosed in the above reference document (1).
Referring to FIGS. 9A through 9E, first, as shown in FIG. 9A, a mask material layer 4 is deposited on a (100)-SOI substrate constructed of a silicon substrate 1, an insulating film 2 and a crystal silicon layer 3 as shown in FIG. 9B, and thereafter a stripe-shaped window is formed in a region where a quantum thin line is to be subsequently formed.
Next, as shown in FIG. 9C, the crystal silicon layer 3 is removed by anisotropic etching while exposing the (111) plane by means of KOH or the like. Subsequently, as shown in FIG. 9D, the mask material layer 4 is removed. Finally, by performing anisotropic etching again by means of KOH or the like as shown in FIG. 9E, a quantum thin line 5 comprised of a triangular prism whose two planes are (111) planes is formed, since the etching rate of the (111) plane is slow relative to the fast etching rate of the (100) plane.
(2) Japanese Patent Laid-Open Publication No. HEI 5-29632.
FIGS. 10A through 10F are process charts showing the "Method for producing Si thin line on Si substrate utilizing anisotropic etching" disclosed in the above reference document (2).
Referring to FIGS. 10A through 10F, first, as shown in FIG. 10A, an etching mask 12 is formed of an silicon oxide film or a silicon nitride film on a silicon (100)-substrate 11. Next, as shown in FIG. 10B, the silicon (100)-substrate 11 is etched by using a silicon anisotropic etchant to form a projecting portion having a triangular cross-section shape.
Next, as shown in FIG. 10C, the etching mask 12 is removed, and after the formation of a silicon nitride film 13, a resist pattern 14 is formed so as to cover the top of the projecting portion. Then, as shown in FIG. 10D, the silicon nitride film 13 and the silicon (100)-substrate 11 are etched by using the resist pattern 14 as a mask.
Next, as shown in FIG. 10E, the resist pattern 14 is removed, and thereafter the silicon (100)-substrate 11 is oxidized. In this case, the silicon nitride film 13 serves as an oxidation-resistant mask, and therefore, a non-oxidized region 15 is left at and around the top of the projecting portion. Finally, as shown in FIG. 10F, if the silicon nitride film 13 is removed, then a silicon thin line (the above-mentioned region) 15 that is insulated and isolated from the silicon (100)-substrate 11 is formed at the top of the projecting portion.
(3) Japanese Patent Laid-Open Publication No. HEI 5-29613.
FIGS. 11A through 11G are process charts showing the "Method for producing Si thin line device during forming gate electrode on Si ridge portion through titanium silicification" disclosed in the above reference document (3).
Referring to FIGS. 11A through 11G, first, as shown in FIG. 11A, a silicon oxide film pattern 22 is formed on a silicon substrate 21. Subsequently, as shown in FIG. 11B, a projecting portion having a triangular cross-section shape is formed by silicon anisotropic etching. Thereafter, as shown in FIG. 1C, the silicon oxide pattern 22 is removed to expose the projecting portion.
Next, as shown in FIG. 11D, oxidation is performed to form a gate insulating film 23. Thereafter, a polysilicon film is deposited and doped with impurities to become a conductive type polysilicon film 24. Further, a titanium film 25 is deposited and thereafter subjected to coating with a resist 27 and etchback. Only a ridge portion 26 of the projecting portion is thus exposed, and the other region is covered with the resist 27. Then, as shown in FIG 11E, the titanium film 25 on the ridge portion 26 of the projecting portion is removed.
Next, as shown in FIG. 11F, after the removal of the resist 27, heat treatment is performed to cause a silicifying reaction, forming a titanium silicide film 28. In this case, a polysilicon film 29 on the ridge portion 26 of the projecting portion is not silicified and left as a polysilicon film. Next, as shown in FIG. 11G, processing is performed with hydrofluoric acid to remove the titanium silicide film 28, as a consequence of which only the polysilicon film 29 on the ridge portion 26 and the gate insulating film 23 are left, forming a gate electrode constructed of a quantum thin line 29. In this case, the top portion facing the gate electrode 29 on the ridge portion 26 is used as a channel region.
However, the conventional quantum thin line forming methods disclosed in the aforementioned reference documents (1) through (3) have the following problems. That is, the reference (1) is the method effective only when the substrate is made of SOI and is not applicable to the conventionally used Si substrate. The SOI substrate costs ten to twenty times the price of the Si substrate, and it is preferable to form the quantum thin line with the Si substrate in order to further reduce the cost.
According to the aforementioned reference (2), the cost can be suppressed low since the Si substrate can be used. However, for the reason that the Si thin line 15 is formed at the top of the Si substrate 11 having a triangular cross-section shape, the surface unevenness of the Si substrate 11 increases. Therefore, the flatness of the surface of the Si substrate 11 becomes degraded, and this results in a difficulty in forming a single-electron transistor.
According to the aforementioned reference (3), for the reason that the Si thin line 29 is formed at the top of the Si substrate 21 having a triangular cross-section shape similarly to the aforementioned reference (2), the surface unevenness of the Si substrate 21 increases. Therefore, the flatness of the surface of the Si substrate 21 becomes degraded, and this results in a difficulty in forming a single-electron transistor. There is a further problem that, since the channel region existing in the ridge portion 26 of the projecting portion is connected with the Si substrate 21, the region cannot be a complete electron confining region.